1. Field of the Invention
The embodiments generally relate to functional testing of a multilayer 3-dimensional integrated circuit (IC), where two separate layers of IC circuits are temporarily connected in order to achieve functionality. More specifically, the embodiments relate to testing a portion of a 3-dimensional IC that is disposed within a chip under test, which includes a first IC layer, by employing a test probe chip including another portion of the 3-dimensional IC in a second IC layer and micro-electrical-mechanical system (MEMS) switches that selectively complete functional circuits, which span the first and second IC layers. Yet more specifically, the MEMS switches include tungsten (W) cone contacts that are formed using a template of graded borophosphosilicate glass (BPSG).
2. Description of Related Art
Three dimensional integrated circuits (ICs) include a number of advantages: shorter interconnects, which provide less delay and require less power; integration of different IC technologies, e.g., separate gallium arsenide (GaAs) and silicon (Si) semiconductor layers; and a smaller form factor. Integration of different IC technologies in a 3-dimensional IC can also include only an n-type metal oxide semiconductor (n-MOS) for a first layer and only a p-type metal oxide semiconductor (p-MOS) for a second layer. Use of separate n-MOS and p-MOS layers for a 3-dimensional IC greatly simplifies wafer processing compared to conventional complementary metal oxide semiconductor (CMOS) processes, which mix n-MOS and p-MOS technologies within a single layer. However, a 3-dimensional CMOS circuit formed from two separate n-MOS and p-MOS layers is only functional when the two n-MOS and p-MOS layers are joined together, i.e., electrically interconnected. Similarly, other 3-dimensional circuits may also provide functionality only when two layers of different IC technologies are electrically interconnected.
For a 3-dimensional circuit with a large die size, i.e., a die size with a less than 90% yield, it is preferable to bond only a good die of one layer to another good die from an adjoining layer in order to avoid losses associated with joining a good die to a bad die. However, functional testing of a circuit within a single layer of a 3-dimensional circuit is not possible, when the functional circuit spans two layers and only a portion of the functional circuit is disposed within the single layer.
There remains a need to functionally test portions of a 3-dimensional integrated circuit (IC) that is disposed within a single layer, before the single layer is permanently joined to a second layer of the 3-dimensional IC.